A 56Gb/s PAM4 Transceiver in 40nm CMOS

by Prof. Jri Lee, Electrical Engineering, National Taiwan University

 :  15 Sep 2017 (Fri)
 :  2:00 - 3:00pm
Venue  :  Rm 2304, 2/F (Lift 17, 18), Academic Complex, HKUST


This talk presents design, fabrication, testing, and analysis of a 56Gb/s PAM4 transceiver for next generation's 400GbE. Realized in 40nm CMOS technology, this design incorporates multiple circuit techniques to achieve high bandwidth and sophisticated signal quality control while consuming only minimum power.


Prof. Jri Lee received the B.Sc. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1995, and the Ph.D. degree in electrical engineering from UCLA, CA, USA, in 2003. He joined National Taiwan University in 2004, where he is currently Professor of electrical engineering. Prof. Lee has received the Beatrice Winner Award, the Takuo Sugano Award, the 10-Year Author Recognition Award at ISSCC, and other international and domestic awards. He also received the NTU Outstanding Teaching Award in 2007, 2008, and 2009. He has served on the Technical Program Committee of ISSCC from 2007 to 2010, and of the Symposium on VLSI Circuits since 2008. He was a guest editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS in 2008. He served as a Distinguished Lecturer of the IEEE Solid-State Circuits Society from 2011 to 2013.