Solutions for Emerging Problems in Core-Based System-on-a-Chip Testing

by Mr. Qiang Xu, PhD Candidate, ECE Department, McMaster University, Ontario, Canada

 :  11 Apr 2005 (Mon)
 :  11:00am - 12:00noon
Venue  :  Room 2404, 2/F (Lifts 17-18), HKUST

This talk addresses several practical and/or emerging problems in testing core-based system-on-a-chip (SOC).

1. Care must be taken to avoid test data corruption for embedded cores with multiple clock domains. This talk shows how at-speed test application can be achieved without test hazards by embedding custom logic in the multi-frequency core wrapper. The introduced limited design-for-testability (DFT) hardware can synchronize the external tester channels with the core's internal scan chains in the shift mode, and provide safe at-speed capture via a careful capture window design.

2. Motivated by the increasing DFT area overhead and potential performance degradation caused by wrapping all the embedded cores for modular SOC testing, we propose a test strategy that can remove the wrapper boundary cells of some critical cores without loss in testability. This new test architecture can be also used for two-pattern test of embedded cores with minor changes, which is necessary to achieve a reliable coverage of delay faults and CMOS stuck-open faults. Novel TAM design and test scheduling algorithms for this new test architecture are also presented.

3. With the increase of reusability, sometimes the older-generation SOCs are themselves used as embedded cores in new SOC designs, thus leading to a hierarchical SOC design paradigm. This talk describes a new framework for TAM design of such hierarchical SOCs. Compared with previous approaches, the proposed method enables system integrators to rapidly tradeoff routing, testing time, DFT area, and test power when selecting a test strategy.

Mr. Xu received the B.E. and M.E. degrees from Beijing University of Posts & Telecommunications, China, in 1997 and 2000, respectively. He is currently a Ph.D candidate at McMaster University, Canada, and expects to finish by June, 2005. Before pursuing his Ph.D degree, he worked at a start-up company in Beijing as an ASIC design engineer and project manager, where he helped to implement its first successful product.

Mr. Xu's research interest lies in system-on-a-chip design and test, where he has published more than 10 papers in referred journals and conferences. He received the Best Paper Award at the 2004 IEEE/ACM Design, Automation, and Test in Europe (DATE) conference and Exhibition.


*** All are Welcome ***