Bio-MEMS
technology for DNA and Cell signal detection
This project is to develop IC based technology to interact with biological material.
The technology can be used in Lab-on-a-chip technology to extract cell
contents and detect the existance of certain DNA fragment. In addition
non-invasive cell based technology to extract cell level signa for drug
profiling is also being pursued.
Nano-CMOS
Transistor Design & Fabrication
The objective is to design and fabricate of CMOS based nano-wire transistors
using top-down manufacturing approach (in contrast to the bottom-up
self-assembly approach developed by Chemist and Physicists) to
extend the scalability of CMOS technology according to the ITRS
Roadmap. The challenge in this project is
the method to form extremely small lines with the limited capability
available in our lab. We
have been studing possible approaches such as oxide trimming, continuous
oxidation and hydrogen annealing to form the silicon nano-wire
transistor.
CMOS Compatible non-volatile technology for RFID
Embedded Non-volatile memory (NVM) is important to store data in
RFID. However, most NVM technology required extract mask and processing
steps in addition to standard CMOS technology. To fulfill the low
cost requirement dictated by the RFID application, we are developing
zero-mask embedded NVM technology and circuit based on standard CMOS
processes.
Phase-Change
Memory Characterization and Modeling
This is a sponsored project by IBM to study and model the driving device characteristics
at the 45nm technology. Studies include diode circuit, double gate, multiple-gate
and surrounding gate MOSFETs.
Multi-gate CMOS Device Modeling
This project is sponsored by NEDO, Japan to develop a compact model
for multi-gate MOSFETs. The model include both the intrinsic devices
and parasitic effects. The complete model will be implemented in
Verilog-A code and release to the public
. This is a join project with Hiroshima University and Peking University.
Power
Management Circuit Design
This is a join project with Prof. Philip Mok to develop power management circuit
in the sub-100nm technology node.